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INTEGRATED CIRCUITS
DATA SHEET
TDA1313; TDA1313T Stereo continuous calibration DAC (CC-DAC)
Objective specification File under Integrated Circuits, IC01 July 1993
Philips Semiconductors
Objective specification
Stereo continuous calibration DAC (CC-DAC)
FEATURES * 4/8 x oversampling (multiplexed/simultaneous input) possible * Voltage output (capable of driving headphone) * Space saving package (SO16 or DIL16) * Low power consumption * Wide dynamic range (16-bit resolution) * Continuous Calibration concept * Easy application: - single 3 to 5.5 V supply rail - output voltage is proportional to the supply voltage - integrated current-to-voltage converter * Internal bias current ensures maximum dynamic range * Wide operating temperature range (-40 C to +85 C) * Compatible with most current Japanese input format multiplexed/simultaneous, two's complement and CMOS) * No zero crossing distortion * Cost efficient * High signal-to-noise ratio * Low total harmonic distortion. ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS TDA1313(1) TDA1313T(2) Notes 1. SOT38-1; 1996 August 15. 2. SOT109-1; 1996 August 15. 16 16 PIN POSITION DIL SO16
TDA1313; TDA1313T
GENERAL DESCRIPTION The TDA1313; 1313T is a voltage driven digital-to-analog converter, and is of a new generation of DACs which incorporates the innovative technique of Continuous Calibration (CC). The largest bit-currents are repeatedly generated from one single current reference source. This duplication is based upon an internal charge storage principle having an accuracy which is insensitive to ageing, temperature and process variations. The TDA1313; 1313T is fabricated in a 1.0 m CMOS process and features an extremely low power dissipation, small package size and easy application. Furthermore, the accuracy of the intrinsic high coarse-current combined with the implemented symmetrical offset decoding method preclude zero-crossing distortion and ensures high quality audio reproduction. Therefore, the CC-DAC is eminently suitable for use in (portable) digital audio equipment.
MATERIAL plastic plastic
CODE SOT38GG SOT109AG
July 1993
2
Philips Semiconductors
Objective specification
Stereo continuous calibration DAC (CC-DAC)
QUICK REFERENCE DATA SYMBOL VDD IDD VFS (THD+N)/S PARAMETER supply voltage supply current full scale output voltage total harmonic distortion plus noise VDD = 5 V; at code 0000H VDD = 5 V at 0 dB signal level at 0 dB signal level; see Fig.8 at -60 dB signal level CONDITIONS - 3.8 - - - - - - at -60 dB; A-weighted - - S/N tCS BR fBCK TCFS signal-to-noise ratio at bipolar zero current setting time to 1LSB input bit rate at data input clock frequency at clock input full scale temperature coefficient at analog outputs (VOL; VOR) operating ambient temperature total power dissipation VDD = 5 V; at code 0000H VDD = 3 V; at code 0000H A-weighted at code 0000H 93 - - - - MIN. 3.0
TDA1313; TDA1313T
TYP. 5.0 8 4.2 -88 0.004 -70 0.03 -36 1.6 -38 1.3 98 0.2 - - 400
MAX. 5.5 9.5 4.6 -81 0.009 - - -28 4.0 - - - - 18.4 18.4 - V
UNIT mA V dB % dB % dB % dB % dB s Mbits/s MHz ppm
Tamb Ptot
-40 - -
- 40 15
+85 53 -
C mW mW
July 1993
3
July 1993
handbook, full pagewidth
Philips Semiconductors
LIN 10 LEFT INPUT REGISTER R2 LEFT OUTPUT REGISTER 4 k 8 OP2 ROUT LEFT BIT SWITCHES RIGHT BIT SWITCHES RIGHT OUTPUT REGISTER C2 1 nF VOR RIGHT INPUT REGISTER
7 RIN
R1
C1 1 nF
4 k
VOL
LOUT 9
OP1
Stereo continuous calibration DAC (CC-DAC)
VREF
11-BIT PASSIVE DIVIDER VREF
32 (5-BIT) CALIBRATED CURRENT SOURCES 11-BIT PASSIVE DIVIDER 1 CALIBRATED SPARE SOURCE 1 CALIBRATED SPARE SOURCE
32 (5-BIT) CALIBRATED CURRENT SOURCES
4
REFERENCE SOURCE CONTROL AND TIMING
3
4/8FSSEL BCK
16
4
VREF C6 1 F
LRSEL/RSI
1
SI/LSI
2
WS 13 C3 100 nF VSSD VDDD VSSO 100 nF VDDO C4 14 5 6
15
TDA1313 TDA1313T
12 C5 100 nF VSSA VDDA 11
MGE230
TDA1313; TDA1313T
Objective specification
Fig.1 Block diagram.
Philips Semiconductors
Objective specification
Stereo continuous calibration DAC (CC-DAC)
PINNING SYMBOL LRSEL/RSI SI/LSI 4/8FSSEL VREF VSSO VDDO RIN ROUT LOUT LIN VDDA VSSA VSSD VDDD WS BCK PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION left/right select; right serial input serial input; left serial input 4/8 oversampling select reference voltage output operational amplifier ground operational amplifier supply voltage right analog input right analog output left analog output left analog input analog supply voltage analog ground digital ground digital supply voltage word select bit clock input
handbook, halfpage
TDA1313; TDA1313T
LRSEL/RSI SI/LSI 4/8FSSEL VREF VSSO VDDO RIN ROUT
1 2 3 4 5 6 7 8
MGE229
16 15 14
BCK WS VDDD
13 VSSD TDA1313 TDA1313T 12 V SSA 11 10 9 VDDA LIN LOUT
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value IREF, the switch S1 is opened and S2 is switched to the other position (Fig.3b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore, the drain current of M1 will still be equal to IREF and this exact duplicate of IREF is now available at the IO terminal. In the TDA1313; 1313T, 32 current sources and one spare current source are continuously calibrated (see Fig.1). The spare current source is included to allow continuous
converter operation. The output of one calibrated source is connected to an 11-bit binary current devider which consists of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching in such a way that the zero-crossing is performed by switching only the LSB currents. The TDA1313; T (CC-DAC) accepts serial input data format of 16 bit word length. The most significant bit (bit 1) must always be first. The timing is illustrated in Fig.4 and the input data formats are illustrated in Figs 5 and 6. Data is placed in the right and left input registers (Fig.1). The data in the input registers is simultaneously latched to the output registers which control the bit switches. VREF and VFS are proportional to VDD. Where: VDD1/VDD2 = VFS1/V = VREF1/VREF2
July 1993
5
Philips Semiconductors
Objective specification
Stereo continuous calibration DAC (CC-DAC)
TDA1313; TDA1313T
handbook, halfpage
IO IREF S2
IO IREF S2 IREF
S1 + Cgs M1 Vgs
S1 + Cgs M1 Vgs
(a)
(b)
MGE231
Fig.3 Calibration principle; (a) calibration (b) operation.
Table 1
Mode application 4/8FSSEL 0 0 1 LRSEL/RSI 1 0 data right MODE 4FS/left = HIGH 4FS/left = LOW 8FS FIGURE 6 6 5
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD TXTAL Tstg Tamb VES PARAMETER supply voltage maximum crystal temperature storage temperature operating ambient temperature electrostatic handling note 1 note 2 Notes 1. Human body model: C = 100 pF; R = 1500 ; 3 zaps positive and negative. 2. Machine model: C = 200 pF; L = 0.5 H; R = 10 ; 3 zaps positive and negative. THERMAL RESISTANCE SYMBOL Rth j-a DIL16 SO16 July 1993 6 PARAMETER from junction to ambient in free air 75 K/W 120 K/W THERMAL RESISTANCE CONDITIONS - - -55 -40 -2000 -200 MIN. 6.0 +150 +150 +85 +2000 +200 MAX. V C C C V V UNIT
Philips Semiconductors
Objective specification
Stereo continuous calibration DAC (CC-DAC)
TDA1313; TDA1313T
CHARACTERISTICS VDDD = VDDA = VDDO = 5 V; Tamb = 25 C; measured in Fig.7; unless otherwise specified. SYMBOL Supply VDD IDD IDDD IDDA IDDO PSRR IIL IIH fBCK BR fWS tr tf tCY tBCKH tBCKL tSU;DAT tHD:DAT tHD:WS tSU;WS supply voltage total supply current digital supply current analog supply current operational amplifier supply current power supply ripple rejection at code 0000H; note 1 - - - - - - - - 54 15 15 12 10 10 12 30 - - - - - - - - - - - - - - - dB A A MHz Mbits/s kHz Digital inputs; pins WS, BCK, 4/8FSSEL, LRSEL/RSI and SI/LSI input leakage current LOW input leakage current HIGH clock frequency bit rate data input word select input frequency VI = 0.V VI = 5.5 V 10 10 18.4 18.4 384 at code 0000H at code 0000H; no clock running 3.0 - - - - 5.0 8.0 0.2 4.6 3.4 5.5 9.5 - 5.5 4 V mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Timing (see Fig.4) rise time fall time bit clock cycle time bit clock pulse width HIGH bit clock pulse width LOW data set-up time data hold time to bit clock word select hold time word select set-up time 12 12 - - - - - - - ns ns ns ns ns ns ns ns ns
July 1993
7
Philips Semiconductors
Objective specification
Stereo continuous calibration DAC (CC-DAC)
SYMBOL PARAMETER CONDITIONS MIN.
TDA1313; TDA1313T
TYP.
MAX.
UNIT
Analog outputs; pins VOL and VOR VFS TCFS RL CL VREF VDC (THD+N)/S full-scale voltage full-scale temperature coefficient load resistance load capacitance reference output voltage output DC voltage total harmonic distortion plus noise at 0 dB signal level; note 2 at 0 dB signal level; see Fig.8 at -60 dB signal level; note 2 at -60 dB signal level; A-weighted; note 2 at 0 dB signal level; f = 20 Hz to 20 kHz tcs IO td S/N Notes 1. Vripple = 1% of the supply voltage; fripple = 100 Hz. 2. Measured with 1 kHz sinewave generated at a sampling rate of 384 kHz. QUALITY SPECIFICATION In accordance with UZW-BO/FQ-0601. current settling time to 1 LSB channel separation see Fig.8 unbalance between outputs time delay between outputs signal-to-noise ratio at bipolar zero A-weighted; at code 0000H note 2 3.8 - 3 - 3.16 2.25 - - - - - - - - - - - 86 - - - 93 4.2 400 - - 3.33 2.5 -88 0.004 -70 0.03 -36 1.6 -38 1.3 -84 0.006 0.2 95 70 0.2 0.2 98 4.6 - - 200 3.5 2.75 -81 0.009 - - -28 4.0 - - -70 0.03 - - - 0.3 - - V ppm k pF V V dB % dB % dB % dB % dB % s dB dB dB s dB
July 1993
8
Philips Semiconductors
Objective specification
Stereo continuous calibration DAC (CC-DAC)
TEST AND APPLICATION INFORMATION
TDA1313; TDA1313T
handbook, full pagewidth
WS tHD; WS >10
tr <12 BCK
tHB >15
tf <12
tLB >15
>12
tSU; WS
tCY >54
tSU; DAT >12
tHD; DAT >10
DATAR DATAL
LSB
MSB
MGE234
SAMPLE OUT
Fig.4 Timing of input signals.
July 1993
9
July 1993
LSB
MGE235
Philips Semiconductors
RSI LSI
MSB
BCK
WS
SAMPLE OUT
Stereo continuous calibration DAC (CC-DAC)
Fig.5 Format of input signals at 8FS.
10
LSB MSB LSB LEFT RIGHT LEFT RIGHT
MGE236
SI
MSB
BCK
WS if LRSEL = 1
WS if LRSEL = 0
SAMPLE OUT
TDA1313; TDA1313T
Objective specification
Fig.6 Format of input signals at 4FS.
Philips Semiconductors
Objective specification
Stereo continuous calibration DAC (CC-DAC)
APPLICATION INFORMATION
TDA1313; TDA1313T
handbook, full pagewidth
10 1 nF VOUTL 200 pF 3 k 9
7 1 nF 8
TDA1313T
3 16 1 2 15 13 14 5 6 12 11 4 22 F 3 k 200 pF
VOUTR
100 nF VDDD
100 nF VDDO
100 nF VDDA
MGE232
Fig.7 TDA1313T as line driver with 3 k/200 pF load.
handbook, full pagewidth
10 8.2 k VOUTL 100 F 32 3 16 1 2 15 13 14 5 6 12 11 2 nF 9
7 2 nF 8 8.2 k 100 F 4 22 F VOUTR 32
TDA1313T
100 nF VDDD
100 nF VDDO
100 nF VDDA
MGE233
Fig.8 TDA1313T as headphone driver with 32 load.
July 1993
11
Philips Semiconductors
Objective specification
Stereo continuous calibration DAC (CC-DAC)
PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body
TDA1313; TDA1313T
SOT38-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT38-1 REFERENCES IEC 050G09 JEDEC MO-001AE EIAJ EUROPEAN PROJECTION A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 3.7 0.15 b 1.40 1.14 0.055 0.045 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 21.8 21.4 0.86 0.84 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.9 3.4 0.15 0.13 ME 8.25 7.80 0.32 0.31 MH 9.5 8.3 0.37 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
ISSUE DATE 92-10-02 95-01-19
July 1993
12
Philips Semiconductors
Objective specification
Stereo continuous calibration DAC (CC-DAC)
SO16: plastic small outline package; 16 leads; body width 3.9 mm
TDA1313; TDA1313T
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 0.24 0.23 L 1.05 0.041 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.0098 0.057 0.069 0.0039 0.049
0.019 0.0098 0.39 0.014 0.0075 0.38
0.028 0.004 0.012
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 91-08-13 95-01-23
July 1993
13
Philips Semiconductors
Objective specification
Stereo continuous calibration DAC (CC-DAC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
TDA1313; TDA1313T
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
July 1993
14
Philips Semiconductors
Objective specification
Stereo continuous calibration DAC (CC-DAC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA1313; TDA1313T
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
July 1993
15

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